1. Field of the Invention
This invention relates to a method for fabricating capacitors, and more particularly, to a method for fabricating crown-shape capacitors by using partial transmission masks. The method begins by using a partial transmission mask, which contains a partial transmission layer, to form a crown-shaped photoresist, then transfers the pattern of the photoresist onto the crown-shaped lower electrode in a capacitor. The method is designed to fabricate crown-shaped capacitors which have larger surface areas than those of stacked capacitors, in order to improve the capacitance of a capacitor.
2. Description of Related Art
Recently, industry has attempted to raise the storage densities of integrated-circuit memories, in order to increase the amount of data that can be saved in a single chip. The cost of every bit of data stored in high-density memory, which is more integrated, is less than the cost of saving the same data in the lower density memory of prior art, which is less integrated. High-density memory provides a higher storage density, which improves efficiency. A conventional method for improving the integration of an integrated circuit is to downsize part of the circuit structure, such as wiring lines, and transistor gates, and shorten the separation between devices. Downsizing part of the circuit structure normally indicates downsizing the design rules for fabricating integrated circuit devices.
A conventional data storage method for DRAM is to selectively charge and discharge each of a series of capacitors formed on the surface of the semiconductor substrate, wherein the charging state corresponds to logic 1 and the discharging state corresponds to logic 0, or vice versa. The amount of charges stored in a capacitor depends on the surface area of the electrodes of the capacitor. The reading and writing operations of a memory cell are processed by selectively connecting the capacitor to a bit line by using a field effect transistor (FET), and then having charges transferred into or retrieved from the capacitor. A contact is placed between the bit line and the FET to link one of the source/drain electrodes of the FET and the bit line while the capacitor makes contact with the other electrode of the FET. The gate of the FET provides the signal in the word line. Connecting the FET and the lower electrode of the capacitor facilitates the transfer of charges between the bit line and the capacitor.
Applying the downsized design rules to DRAM decreases the substrate surface area provided for forming capacitor surfaces of a DRAM. Furthermore, applying the downsized design rules to the conventional, 2-dimentional design of the capacitor reduces the number of charges that can be stored in a capacitor, i.e. static permittivity. Reducing the permittivity leads to several problems including loss of stored information, because the capacitor is very sensitive to decay mechanisms and charge leakage. Sensitivity to charge leakage results in a DRAM needing a faster refresh rate, which causes another problem in that the memory cell cannot store or retrieve information while the memory cell is being refreshed. Therefore, reducing the permittivity requires either a more complicated design for reading and retrieving information or more sensitive signal amplifiers. Furthermore, the newest DRAM designs require higher permittivity from the tiny surface of a DRAM cell.
Conventionally, the DRAM fabrication process for a capacity less than 1 MB (10.sup.6 bytes) normally uses 2-dimensional capacitors or so-called planar-type capacitors. Since the planar-type capacitor requires a relatively large area on the substrate for storing charges, it is not suitable for a more highly integrated design. For a more highly integrated DRAM having a capacity of 4 MB or greater, a 3-dimensional capacitor such as a stacked-type capacitor is required.
Compared with the planar-type capacitor, a stacked-type capacitor has a relatively high permittivity because the size of the memory cell has been further reduced. However, as the integration of a DRAM towards a DRAM with a capacity of 64 MB, a simple 3-dimensional capacitor can no longer meet the demands placed on it.
One solution is to horizontally extend and stack the electrodes and the dielectric layer of a capacitor to form a fin-type stacked capacitor that increases permittivity by increasing the surface of the capacitor. Information related to forming a fin-type capacity can be found in "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs" [International Electron Devices Meeting, pp592-595, December 1988] by Ema, U.S. Pat. Nos. 5071783, 5126810, and 5206787.
Another solution is to vertically extend the electrodes and dielectric layer of a capacitor to form a so-called crown-shaped capacitor that increases permittivity by increasing the surface area of the capacitor.
A conventional method for fabricating crown-shape capacitor is shown in FIGS. 1A through 1H.
Referring to FIG. 1A, first a FET 102 is formed on the substrate 100, wherein the FET includes a gate 104 and source/drain regions 106 which are formed on the active area of the substrate, and are isolated by field oxide 101. Then, a dielectric layer 108, an etching stop layer 110 and a dielectric layer 118 are formed in sequence on the substrate 100. Chemical vapor deposition (CVD) or borophosphosilicate glass (BPSG) can be employed to deposit a SiO2 layer on the tops of the substrate 100 and etching stop layer 110 with the result that dielectric layers 108 and 118 both include SiO.sub.2 layers. Etching stop layer 110 includes silicon nitride, which can be formed by employing CVD to deposit a silicon nitride layer on the top of the dielectric layer 108. Then, a photoresist layer 120 is coated on top of dielectric layer 118, and shaped into a defined photoresist layer by employing a photolithography process, wherein the defined photoresist 120 is used to define an area in which the deep pattern is formed.
Referring next to FIG. 1B, the dielectric layer 118a, etching stop layer 110a, and dielectric layer 108a are etched through in sequence by utilizing the photoresist layer 120 as a mask. Because oxide and nitride have nearly identical etching rates, a low selectivity etching process on oxide and nitride is used. A deep opening 121 is formed in the dielectric layer 108a, the etching stop layer 110a, and the dielectric layer 118a in order to expose one of the source/drain regions 106 underneath. Since the high aspect ratio is high, deviation is likely to happen in the etching process, and the etching depth is difficult to control. Furthermore, although a prolonged etching period is necessary in order to etch through the thick dielectric layer, serious damage to photoresist layer 120 results, which decreases the latter's efficiency as an etching stop. This decreases device yield.
Referring to FIG. 1C, another photoresist layer 130 is formed to define the desired shallow patterns after the photoresist layer is removed, wherein the photoresist layer 130 exposes the previously formed deep opening 121, and the shallow pattern has a larger horizontal dimension than that of the deep pattern.
Referring next to FIG. 1D, an opening 121b with a large horizontal dimension is formed on the dielectric layer 118b above the etching stop layer 110a by performing a dry etching process with a high etching selectivity process on oxide and nitride, and using the photoresist layer 130 as the etching mask. During the shallow etching process, the previously formed deep opening 121 is also etched, as a result, the opening 121a is over-etched, furthermore, the conductivity of the device is impaired by the damage to the source/drain regions 106 due to etching.
Referring to FIG. 1E, the photoresist 130 is then removed.
Referring next to FIG. 1F, a conductive layer 122 is formed on the substrate 100. The opening 121a is filled up with the same conductive material forming the conductive layer 122, the surface 127 of the larger opening 121b is covered by the conductive material as well. The conductive material used in this step includes polysilicon. Generally, dopants are implanted into polysilicon for increasing the conductivity.
Referring to FIG. 1G, a planarization process is performed using, for example, chemical-mechanical polishing on the conductive layer 122 to expose the surface of the dielectric layer 118b. Then, the dielectric layer 118b is removed to expose the profile of a lower electrode 122a of a capacitor.
Referring next to FIG. 1H, a dielectric film 124 is formed on the surface of the lower electrode 122a, thereafter, the dielectric film 124 is covered by a conductive layer 132 in order to construct an upper electrode of a capacitor.
Because the conventional method for fabricating the crown-shaped capacitors of a DRAM is very complicated, it is both time-consuming and costly.